In many silicon foundry processes above 90 nm, the memory cells often have a low aspect ratio, e.g., the cells are tall and skinny in order to limit or decrease the effects of driving polysilicon wordlines across the width of the memory array. However, in many processes under 90 nm, foundries may typically provide memory cells that have a high aspect ratio, e.g., the cells are wide and short. This is typically because wide cells (having a high aspect ratio) may be easier to manufacture for deep submicron processes because, for example, the these cells can accommodate polysilicon and diffusion areas that runs in a single direction, may be assembled in a smaller footprint (e.g., allowing denser memory arrays in some cases) and/or may have a lower bitline capacitance at these geometries in some cases. Also, different foundries may use either of the two aspect ratios depending on the maturity of their process technology.
For systems, such as microprocessors, embedded processors, processor system on chips (SOCs) and others, companies may desire faster frequencies and higher levels of chip integration that smaller process geometries may provide, and Integrated Circuit (IC) companies may often desire faster time-to-market to satisfy these requests or demands. However, process migration for memory arrays may provide a significant challenge since the periphery circuitry (e.g., wiring, address decoders, wordline drivers, column muxes, sense amps, precharge circuits, I/O and datapath circuitry, and the like) for the memory circuit may often be custom designed and may even pitch-matched or otherwise tailored (e.g., in one or more respects) to the size or aspect ratio of the memory cell being used. Thus, at least in some cases, a change in the memory cell size or aspect ratio may often require significant changes in the periphery circuitry for the memory circuit, which may add expense and introduce further delay in completing a product.